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SH7713 Datasheet(PDF) 218 Page - Renesas Technology Corp |
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SH7713 Datasheet(HTML) 218 Page - Renesas Technology Corp |
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218 / 904 page ![]() Section 4 Exception Handling Rev.1.50 Aug. 30, 2006 Page 178 of 860 REJ09B0288-0150 CPU Address Error in Repeat Control Period: If a CPU address error occurs in the repeat control period, the exception is accepted but an exception code (H'070) indicating the repeat loop period is specified in the EXPEVT. If a CPU address error occurs in instructions following a repeat detection instruction to repeat end instruction, an exception code for instruction access or data access is specified in the EXPEVT. The SPC is saved according to the description in section 4.4.3, Exception in Repeat Control Period. After the CPU address error exception processing, the repeat control cannot be returned correctly. To execute a repeat loop correctly, care must be taken not to generate a CPU address error in the repeat control period. Note: In a repeat loop consisting of one to three instructions, some restrictions apply to repeat detection instructions and all the remaining instructions. In a repeat loop consisting of four or more instructions, restrictions apply to only the four instructions that include a repeat end instruction. The restriction occurs when SR.RC[11:0] ≥ 1. Table 4.5 Instruction Where a Specific Exception Occurs when Memory Access Exception Occurs in Repeat Control (SR.RC[11:0] ≥ 1) Number of Instructions in Repeat Loop Instruction where Exception Occurs 1 2 3 4 or Greater RptDtct RptDtct1 Instruction/data access Instruction/data access Instruction/data access Instruction/data access RptDtct2 Instruction/data access Instruction/data access Instruction/data access RptDtct3 Instruction/data access Instruction/data access Note: The following labels are used here. RptDtct: Repeat detection instruction RptDtct1: An instruction of one instruction following the repeat detection instruction RptDtct2: An instruction of two instruction following the repeat detection instruction RptDtct3: An instruction of three instruction following the repeat detection instruction |
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