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SH7713 Datasheet(PDF) 301 Page - Renesas Technology Corp |
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SH7713 Datasheet(HTML) 301 Page - Renesas Technology Corp |
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301 / 904 page ![]() Section 8 Interrupt Controller (INTC) Rev.1.50 Aug. 30, 2006 Page 261 of 860 REJ09B0288-0150 I3 to I0: Interrupt mask bits in status register (SR) Program execution state Interrupt generated? SR.BL=0 or sleep mode? Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No NMI? Level 15 interrupt? Set interrupt source in INTEVT, INTEVT2 Save SR to SSR; save PC to SPC Set BL/MD/RB bit in SR to 1 Branch to exception handler I3 to I0 level 14 or lower? Level 14 interrupt? I3 to I0 level 13 or lower? Level 1 interrupt? I3 to I0 level 0? Figure 8.3 Interrupt Operation Flowchart |
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