SH7721 datasheet(412/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 9

Bus State Controller (BSC)

Rev. 3.00 Jan. 18, 2008 Page 350 of 1458

REJ09B0033-0300

Table 9.12

Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and

Address Multiplex Output (1)-2

Setting

A2/3

BSZ

[1:0]

A2/3

ROW

[1:0]

A2/3

COL

[1:0]

11 (32 bits)

01 (12 bits)

00 (8 bits)

Output Pin of

This LSI

Row Address

Output

Column Address

Output

Synchronous

DRAM Pin

Function

A17

A24

A17

A16

A23

A16

Unused

A15

A23*

A13 (BA1)

A14

A22*

A12 (BA0)

Specifies bank

A13

A21

A13

A11

Address

A12

A20

L/H*

A10/AP

Specifies

address/precharge

A11

A19

A11

A10

A18

A10

A17

A16

A15

A14

A13

A12

A11

A10

Address

Unused

Example of connected memory

128-Mbit product (1 Mword x 32 bits x 4 banks, column 8 bits product): 1

64-Mbit product (1 Mword x 16 bits x 4 banks, column 8 bits product): 2

Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the

access mode.

2. Bank address specification

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