SH7721 datasheet(415/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 9

Bus State Controller (BSC)

Rev. 3.00 Jan. 18, 2008 Page 353 of 1458

REJ09B0033-0300

Table 9.14

Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and

Address Multiplex Output (3)

Setting

A2/3

BSZ

[1:0]

A2/3

ROW

[1:0]

A2/3

COL

[1:0]

11 (32 bits)

10 (13 bits)

01 (9 bits)

Output Pin of

This LSI

Row Address

Output

Column Address

Output

Synchronous

DRAM Pin

Function

A17

A26

A17

Unused

A16

A25*

A14 (BA1)

A15

A24*

A13 (BA0)

Specifies bank

A14

A23

A14

A12

A13

A22

A13

A11

Address

A12

A21

L/H*

A10/AP

Specifies

address/precharge

A11

A20

A11

A10

A19

A10

A18

A17

A16

A15

A14

A13

A12

A11

Address

A10

Unused

Example of connected memory

512-Mbit product (4 Mwords x 32 bits x 4 banks, column 9 bits product): 1

256-Mbit product (4 Mwords x 16 bits x 4 banks, column 9 bits product): 2

Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the

access mode.

2. Bank address specification

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