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SH7721 Datasheet(PDF) 418 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 418 Page - Renesas Technology Corp |
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418 / 1524 page ![]() Section 9 Bus State Controller (BSC) Rev. 3.00 Jan. 18, 2008 Page 356 of 1458 REJ09B0033-0300 Table 9.16 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address Multiplex Output (5)-1 Setting A2/3 BSZ [1:0] A2/3 ROW [1:0] A2/3 COL [1:0] 10 (16 bits) 01 (12 bits) 01 (9 bits) Output Pin of This LSI Row Address Output Column Address Output Synchronous DRAM Pin Function A17 A26 A17 A16 A25 A16 A15 A24 A15 Unused A14 A23* 2 A23* 2 A13 (BA1) A13 A22* 2 A22* 2 A12 (BA0) Specifies bank A12 A21 A12 A11 Address A11 A20 L/H* 1 A10/AP Specifies address/precharge A10 A19 A10 A9 A9 A18 A9 A8 A8 A17 A8 A7 A7 A16 A7 A6 A6 A15 A6 A5 A5 A14 A5 A4 A4 A13 A4 A3 A3 A12 A3 A2 A2 A11 A2 A1 A1 A10 A1 A0 Address A0 A9 A0 Unused Example of connected memory 128-Mbit product (2 Mwords x 16 bits x 4 banks, column 9 bits product): 1 Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the access mode. 2. Bank address specification |
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