SH7721 datasheet(446/1524 Pages) RENESAS

446 / 1524 page

Section 9

Bus State Controller (BSC)

Rev. 3.00 Jan. 18, 2008 Page 384 of 1458

REJ09B0033-0300

CKIO

A25 to A0

CSn

RD/

RAS

DQMxx

D31 to D0

Tpw

DACKn*4

Trr

A12/A11*3

BA1*1

BA0*2

CAS

1. Address pin to be connected to the BA1 pin of SDRAM.

2. Address pin to be connected to the BA0 pin of SDRAM.

3. Address pin to be connected to the A10 pin of SDRAM.

4. The waveform for DACKn is when active low is specified.

Trc

Tmw

Hi-Z

Tnop

Trc

Trr

Trc

REF

MRS

Temw

Tnop

EMRS

PALL

Notes:

Figure 9.29

EMRS Command Issue Timing

• Deep power-down mode

The low-power SDRAM supports the deep power-down mode as a low-power consumption

mode. In the partial self-refresh function, self-refresh is performed on a specific area. In the

deep power-down mode, self-refresh will not be performed on any memory area. This mode is

effective in systems where all of the system memory areas are used as work areas.

If the RMODE bit of the SDCR is set to 1 while the DEEP and RFSH bits of the SDCR are set to

1, the low-power SDRAM enters the deep power-down mode. If the RMODE bit is cleared to 0,

the CKE signal is pulled high to cancel the deep power-down mode. Before executing an access

after returning from the deep power-down mode, the power-up sequence must be re-executed.

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