SH7721 datasheet(443/1524 Pages) RENESAS

443 / 1524 page

Section 9

Bus State Controller (BSC)

Rev. 3.00 Jan. 18, 2008 Page 381 of 1458

REJ09B0033-0300

Mode register setting timing is shown in figure 9.28. A PALL command (all bank precharge

command) is firstly issued. A REF command (auto-refresh command) is then issued 8 times. An

MRS command (mode register write command) is finally issued. Idle cycles, of which number is

specified by the TRP[1:0] bits in CSnWCR, are inserted between the PALL and the first REF. Idle

cycles, of which number is specified by the TRC[1:0]bits in CSnWCR, are inserted between REF

and REF, and between the 8th REF and MRS. Idle cycles, of which number is one or more, are

inserted between the MRS and a command to be issued next.

It is necessary to keep idle time of certain cycles for SDRAM before issuing PALL command after

power-on. Refer the manual of the SDRAM for the idle time to be needed. When the pulse width

of the reset signal is longer then the idle time, mode register setting can be started immediately

after the reset, but care should be taken when the pulse width of the reset signal is shorter than the

idle time.

CKIO

A25 to A0

CSn

RD/

RAS

DQMxx

D31 to D0

Tpw

DACKn*2

Trr

A12/A11*1

CAS

1. Address pin to be connected to the A10 pin of SDRAM.

2. The waveform for DACKn is when active low is specified.

Trc

Tmw

Hi-Z

Tnop

Trc

Trr

Trc

REF

MRS

PALL

Notes:

Figure 9.28

Write Timing for SDRAM Mode Register (Based on JEDEC)

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