SH7721 datasheet(441/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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441 / 1524 page

Section 9

Bus State Controller (BSC)

Rev. 3.00 Jan. 18, 2008 Page 379 of 1458

REJ09B0033-0300

(11) Power-On Sequence

In order to use SDRAM, mode setting must first be performed after powering on. To perform

SDRAM initialization correctly, the bus state controller registers must first be set, followed by a

write to the SDRAM mode register. In SDRAM mode register setting, the address signal value at

that time is latched by a combination of the

CSn, RAS, CAS, and RD/WR signals. If the value to

be set is X, the bus state controller provides for value X to be written to the SDRAM mode

H'A4FD5000 + X for area 3 SDRAM. In this operation the data is ignored, but the mode write is

performed as a byte-size access. To set burst read/single write, CAS latency 2 to 3, wrap type =

sequential, and burst length 1 supported by the LSI, arbitrary data is written in a byte-size access

to the addresses shown in table 9.19. In this time 0 is output at the external address pins of A12 or

later.

SH7721 Datasheet(PDF) 441 Page - Renesas Technology Corp