SH7721 datasheet(437/1524 Pages) RENESAS

437 / 1524 page

Section 9

Bus State Controller (BSC)

Rev. 3.00 Jan. 18, 2008 Page 375 of 1458

REJ09B0033-0300

CKIO

A25 to A0

CSn

RD/

D31 to D0

Tpw

DACKn*2

Trr

A12/A11*1

Trc

Hi-z

RAS

DQMxx

CAS

1. Address pin to be connected to the A10 pin of SDRAM.

2. The waveform for DACKn is when active low is specified.

Notes:

Figure 9.25

Auto-Refresh Timing

(b)

Self-refreshing

Self-refresh mode in which the refresh timing and refresh addresses are generated within the

SDRAM. Self-refreshing is activated by setting both the RMODE bit and the RFSH bit in SDCR

to 1. After starting the self-refreshing, PALL command is issued in Tp cycle after the completion

of the pre-charging bank. A SELF command is then issued after inserting idle cycles of which

number is specified by the TRP[1:0] bits in CSnWSR. SDRAM cannot be accessed while in the

self-refresh state. Self-refresh mode is cleared by clearing the RMODE bit to 0. After self-refresh

mode has been cleared, command issuance is disabled for the number of cycles specified by the

TRC[1:0] bits in CSnWCR.

Self-refresh timing is shown in figure 9.26. Settings must be made so that self-refresh clearing and

data retention are performed correctly, and auto-refreshing is performed at the correct intervals.

When self-refreshing is activated from the state in which auto-refreshing is set, or when exiting

standby mode other than through a power-on reset, auto-refreshing is restarted if the RFSH bit is

set to 1 and the RMODE bit is cleared to 0 when self-refresh mode is cleared. If the transition

from clearing of self-refresh mode to the start of auto-refreshing takes time, this time should be

SH7721 Datasheet(PDF) 437 Page - Renesas Technology Corp