SH7721 datasheet(438/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

PDF	1524 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 9

Bus State Controller (BSC)

Rev. 3.00 Jan. 18, 2008 Page 376 of 1458

REJ09B0033-0300

taken into consideration when setting the initial value of RTCNT. Making the RTCNT value 1 less

than the RTCOR value will enable refreshing to be started immediately.

After self-refreshing has been set, the self-refresh state continues even if the chip standby state is

entered using the LSI standby function, and is maintained even after recovery from standby mode

by an interrupt.

The self-refresh state is not cleared by a manual reset.

In case of a power-on reset, the bus state controller's registers are initialized, and therefore the

self-refresh state is cleared.

CKIO

A25 to A0

CSn

RD/

D31 to D0

Tpw

DACKn*2

Trr

A12/A11*1

Trc

Hi-z

Trc

CKE

RAS

DQMxx

CAS

1. Address pin to be connected to the A10 pin of SDRAM.

2. The waveform for DACKn is when active low is specified.

Notes:

Figure 9.26

Self-Refresh Timing

SH7721 Datasheet(PDF) 438 Page - Renesas Technology Corp