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SH7721 Datasheet(PDF) 440 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 440 Page - Renesas Technology Corp |
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440 / 1524 page  Section 9 Bus State Controller (BSC) Rev. 3.00 Jan. 18, 2008 Page 378 of 1458 REJ09B0033-0300 (10) Power-Down Mode If the PDOWN bit in SDCR is set to 1, the SDRAM is placed in the power-down mode by bringing the CKE signal to the low level in the non-access cycle. This power-down mode can effectively lower the power consumption in the non-access cycle. However, please note that if an access occurs in power-down mode, a cycle of overhead occurs because a cycle that asserts the CKE in order to cancel power-down mode is inserted. Figure 9.27 shows the access timing in power-down mode. CKIO A25 to A0 CSn RD/ WR D31 to D0 BS Tnop DACKn*2 Power-down Tr A12/A11*1 Tc1 Td1 Tde Tap Power-down CKE RAS DQMxx CAS 1. Address pin to be connected to the A10 pin of SDRAM. 2. The waveform for DACKn is when active low is specified. Notes: Figure 9.27 Access Timing in Power-Down Mode |
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