SH7721 datasheet(444/1524 Pages) RENESAS

444 / 1524 page

Section 9

Bus State Controller (BSC)

Rev. 3.00 Jan. 18, 2008 Page 382 of 1458

REJ09B0033-0300

(12) Low-Power SDRAM

The low-power SDRAM can be accessed using the same protocol as the normal SDRAM. The

differences between the low-power SDRAM and normal SDRAM are that partial refresh takes

place that puts only a part of the SDRAM in the self-refresh state during the self-refresh function,

and that power consumption is low during refresh under user conditions such as the operating

temperature. The partial refresh is effective in systems in which data in a work area other than the

specific area can be lost without severe repercussions. For details, refer to the data sheet for the

low-power SDRAM to be used.

The low-power SDRAM supports the extension mode register (EMRS) in addition to the mode

registers as the normal SDRAM. This LSI supports issuing of the EMRS command.

The EMRS command is issued according to the conditions specified in table 9.20. For example, if

data H'0YYYYYYY is written to address H'A4FD5XXX in long-word, the commands are issued

to the CS3 space in the following sequence: PALL -> REF

× 8 -> MRS -> EMRS. In this case, the

MRS and EMRS issue addresses are H'0000XXX and H'YYYYYYY, respectively. If data

H'1YYYYYYY is written to address H'A4FD5XXX in long-word, the commands are issued to the

CS3 space in the following sequence: PALL -> MRS -> EMRS.

SH7721 Datasheet(PDF) 444 Page - Renesas Technology Corp