SH7721 datasheet(571/1524 Pages) RENESAS

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Section 14 Timer Unit (TMU)

Rev. 3.00 Jan. 18, 2008 Page 509 of 1458

REJ09B0033-0300

14.4.3

Interrupt Sources and Priorities

The TMU generates underflow interrupts for each channel. When the interrupt request flag and

interrupt enable bit are both set to 1, the interrupt is requested. Codes are set in the interrupt event

according to the codes.

The relative priorities between channels can be changed using the interrupt controller. For details,

refer to section 7, Exception Handling, and section 8, Interrupt Controller (INTC). Table 14.1 lists

TMU interrupt sources.

Table 14.1

TMU Interrupt Sources

Channel

Interrupt Source

Description

Priority

TUNI0

Underflow interrupt 0

High

TUNI1

Underflow interrupt 1

TUNI2

Underflow interrupt 2

Low

Software standby mode can be cancelled by TSU_SUNI which is OR of an underflow interrupt for

each TMU channel. (It is available when the RTC output clock is selected as a counter input

clock.)

TMU_SUNI is processed as an interrupt which differs from an underflow interrupt for each

channel by the interrupt controller (INTC). Therefore, an underflow interrupt for each channel and

TMU_SUNI should be used differently.

When canceling software standby mode, set the bits 11 to 8 in interrupt priority register D (IPRD)

of INTC to any value and bits 15 to 4 in interrupt priority register A (IPRA) of INTC to H'000 so

that only the TMU_SUNI is accepted. In the TMU_SUNI interrupt routine, clear both the under

flow flag (UNF) in the timer control register (TCR) and the TMU_SUNI interrupt request bit

(TMU_SUNIR) in the interrupt request register 0 of INTC.

In the normal operating state, set the bits 11 to 8 in IPRD to H'0 and bits 15 to 4 in IPRA to any

value so that an underflow interrupt can be accepted for each channel. For details, see section 8,

Interrupt Controller (INTC).

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