SH7721 datasheet(573/1524 Pages) RENESAS

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Section 15

16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Jan. 18, 2008 Page 511 of 1458

REJ09B0033-0300

Section 15

16-Bit Timer Pulse Unit (TPU)

This LSI has an on-chip 16-bit timer pulse unit (TPU) that comprises four 16-bit timer channels.

15.1

Features

• Maximum 4-pulse output

 A total of 16 timer general registers (TGRA to TGRD × 4 ch.) are provided (four each for

channels). TGRA can be set as an output compare register.

 TGRB, TGRC, and TGRD for each channel can also be used as timer counter clearing

registers. TGRC and TGRD can also be used as buffer registers.

• Selection of four counter input clocks for channels 0 and 1, and of six counter input clocks for

channels 2 and 3.

• The following operations can be set for each channel:

 Waveform output at compare match: Selection of 0, 1, or toggle output

 Counter clear operation: Counter clearing possible by compare match

 PWM mode: Any PWM output duty can be set

Maximum of 4-phase PWM output possible

• Buffer operation settable for each channel

 Automatic rewriting of output compare register possible

• Phase counting mode settable independently for each of channels 2, and 3

 Two-phase encoder pulse up/down-count possible

• An interrupt request for each channel

 For channels 0 and 1, compare match interrupts and overflow interrupts can be requested

independently

 For channels 2, and 3, compare match interrupts, overflow interrupts, and underflow

interrupts can be requested independently

Table 15.1 lists the functions of the TPU.

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