SH7721 datasheet(577/1524 Pages) RENESAS

577 / 1524 page

Section 15

16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Jan. 18, 2008 Page 515 of 1458

REJ09B0033-0300

15.3

The TPU has the following registers. Refer to section 37, List of Registers, for more details on the

addresses and states of these registers in each operating mode.

Channel 0:

• Timer control register_0 (TCR_0)

• Timer mode register_0 (TMDR_0)

• Timer I/O control register_0 (TIOR_0)

• Timer interrupt enable register_0 (TIER_0)

• Timer status register_0 (TSR_0)

• Timer counter_0 (TCNT_0)

• Timer general register A_0 (TGRA_0)

• Timer general register B_0 (TGRB_0)

• Timer general register C_0 (TGRC_0)

• Timer general register D_0 (TGRD_0)

Channel 1:

• Timer control register_1 (TCR_1)

• Timer mode register_1 (TMDR_1)

• Timer I/O control register_1 (TIOR_1)

• Timer interrupt enable register_1 (TIER_1)

• Timer status register_1 (TSR_1)

• Timer counter_1 (TCNT_1)

• Timer general register A_1 (TGRA_1)

• Timer general register B_1 (TGRB_1)

• Timer general register C_1 (TGRC_1)

• Timer general register D_1 (TGRD_1)

Channel 2:

• Timer control register_2 (TCR_2)

• Timer mode register_2 (TMDR_2)

• Timer I/O control register_2 (TIOR_2)

• Timer interrupt enable register_2 (TIER_2)

• Timer status register_2 (TSR_2)

SH7721 Datasheet(PDF) 577 Page - Renesas Technology Corp