SH7721 datasheet(579/1524 Pages) RENESAS

579 / 1524 page

Section 15

16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Jan. 18, 2008 Page 517 of 1458

REJ09B0033-0300

Bit

Bit Name

Initial

Value

R/W

Description

15 to 8



All 0

Reserved

These bits are always read as 0 and cannot be modified.

CCLR2

CCLR1

CCLR0

R/W

Counter Clear 2, 1, and 0

These bits select the TCNT counter clearing source.

000: TCNT clearing disabled

001: TCNT cleared by TGRA compare match

010: TCNT cleared by TGRB compare match

011: Reserved (setting prohibited)

100: TCNT clearing disabled

101: TCNT cleared by TGRC compare match

110: TCNT cleared by TGRD compare match

111: Reserved (setting prohibited)

CKEG1

CKEG0

R/W

Clock Edge 1 and 0

These bits select the input clock edge. When the input clock

is counted using both edges, the input clock period is halved

(e.g.

φ/4 both edges = φ/2 rising edge). If phase counting

mode is used this setting is ignored.

00: Count at rising edge

01: Count at falling edge

1X: Count at both edges*

[Legend] X: Don't care

Note: * If P

φ/1 is selected for the input clock, operation is

disabled.

TPSC2

TPSC1

TPSC0

R/W

Time Prescaler 2, 1, and 0

These bits select the TCNT counter clock. The clock source

can be selected independently for each channel. Table 15.3

shows the clock sources that can be set for each channel.

For more in formation on count clock selection, see table

15.4.

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