SH7721 datasheet(583/1524 Pages) RENESAS

583 / 1524 page

Section 15

16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Jan. 18, 2008 Page 521 of 1458

REJ09B0033-0300

Bit

Bit Name

Initial

Value

R/W

Description

MD2

MD1

MD0

R/W

Modes 2 to 0

These bits are used to set the timer operating mode.

000: Normal operation

001: Reserved (setting prohibited)

010: PWM mode

011: Reserved (setting prohibited)

100: Phase counting mode 1

101: Phase counting mode 2

110: Phase counting mode 3

111: Phase counting mode 4

Note:

Operation when setting (BFWT, BFB, BFA) = (1, 1, 0) is the same as when setting

(BFWT, BFB, BFA) = (1, 0, 1). However, when the BFB bit is set to 1 (TGRB and TGRD

used together for buffer operation), the setting of (BFWT, BFB, BFA) = (1, 1, 1) should

be made. In this case, the value set in TGRA should also be set in TGRC because

TGRA and TGRC are also used together for buffer operation.

15.3.3

Timer I/O Control Registers (TIOR)

The TIOR registers are 16-bit registers that control the TPU_TO pin. The TPU has four TIOR

registers, one for each channel. The TIOR registers are initialized to H'0000 by a reset, but not

initialized in standby mode, sleep mode, or module standby.

TIOR register settings should be made only when TCNT operation is halted.

Care is required since TIOR is affected by the TMDR setting.

If the counting operation is halted, the initial value set by this register is output from the TPU_TO

pin.

SH7721 Datasheet(PDF) 583 Page - Renesas Technology Corp