SH7721 datasheet(586/1524 Pages) RENESAS

586 / 1524 page

Section 15

16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Jan. 18, 2008 Page 524 of 1458

REJ09B0033-0300

Bit

Bit Name

Initial

Value

R/W

Description

TG1EB

R/W

TGR Interrupt Enable B

Enables or disables interrupt requests by the TGFB bit when

the TGFB bit in TSR is set to 1 (TCNT and TGRB compare

match).

0: Interrupt requests by TGFB disabled

1: Interrupt requests by TGFB enabled

TG1EA

R/W

TGR Interrupt Enable A

Enables or disables interrupt requests by the TGFA bit when

the TGFA bit in TSR is set to 1 (TCNT and TGRA compare

match).

0: Interrupt requests by TGFA disabled

1: Interrupt requests by TGFA enabled

15.3.5

Timer Status Registers (TSR)

The TSR registers are 16-bit registers that indicate the status of each channel. The TPU has four

TSR registers, one for each channel. The TSR registers are initialized to H'0000 by a reset, but not

initialized in standby mode, sleep mode or module standby mode.

Bit

Bit Name

Initial

Value R/W

Description

15 to 8



All 0

Reserved

These bits are always read as 0 and cannot be modified.

TCFD

Count Direction Flag

Status flag that shows the direction in which TCNT counts in

phase counting mode of channels 2, and 3.

In channels 0 and 1, bit 7 is reserved. It is always read as 0

and cannot be modified.

0: TCNT counts down

1: TCNT counts up



Reserved

This bit is always read as 0 and cannot be modified.

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