SH7721 datasheet(585/1524 Pages) RENESAS

585 / 1524 page

Section 15

16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Jan. 18, 2008 Page 523 of 1458

REJ09B0033-0300

15.3.4

Timer Interrupt Enable Registers (TIER)

The TIER registers are 16-bit registers that control enabling or disabling of interrupt requests for

each channel. The TPU has four TIER registers, one for each channel. The TIER registers are

initialized to H'0000 by a reset, but not initialized in standby mode, sleep mode or module

standby.

Bit

Bit Name

Initial

Value

R/W

Description

15 to 6



Reserved

These bits are always read as 0 and cannot be modified.

TC1EU

R/W

Underflow Interrupt Enable

Enables or disables interrupt requests by the TCFU bit when

the TCFU bit in TSR is set to 1 in phase counting mode of

channels 2, and 3 (TCNT underflow).

In channels 0 and 1, bit 5 is reserved. It is always read as 0

and cannot be modified.

0: Interrupt requests by TCFU disabled

1: Interrupt requests by TCFU enabled

TC1EV

R/W

Overflow Interrupt Enable

Enables or disables interrupt requests by the TCFV bit when

the TCFV bit in TSR is set to 1 (TCNT overflow).

0: Interrupt requests by TCFV disabled

1: Interrupt requests by TCFV enabled

TG1ED

R/W

TGR Interrupt Enable D

Enables or disables interrupt requests by the TGFD bit when

the TGFD bit in TSR is set to (TCNT and TGRD compare

match).

0: Interrupt requests by TGFD disabled

1: Interrupt requests by TGFD enabled

TG1EC

R/W

TGR Interrupt Enable C

Enables or disables interrupt requests by the TGFC bit when

the TGFC bit in TSR is set to 1 (TCNT and TGRC compare

match).

0: Interrupt requests by TGFC disabled

1: Interrupt requests by TGFC enabled

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