SH7721 datasheet(582/1524 Pages) RENESAS

582 / 1524 page

Section 15

16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Jan. 18, 2008 Page 520 of 1458

REJ09B0033-0300

15.3.2

Timer Mode Registers (TMDR)

The TMDR registers are 16-bit readable/writable registers that are used to set the operating mode

for each channel. The TPU has four TMDR registers, one for each channel. The TMDR registers

are initialized to H'0000 by a reset, but not initialized in standby mode, sleep mode, or module

standby.

TMDR register settings should be made only when TCNT operation is stopped.

Bit

Bit Name

Initial

Value

R/W

Description

15 to 7



All 0

Reserved

These bits are always read as 0 and cannot be modified.

BFWT

R/W

Buffer Write Timing

Specifies TGRA and TGRB update timing when TGRC and

TGRD are used as a compare match buffer. When TGRC

and TGRD are not used as a compare match buffer register,

this bit does not function.

0: TGRA and TGRB are rewritten at compare match of each

1: TGRA and TGRB are rewritten in counter clearing.

BFB

R/W

Buffer Operation B

Specifies whether TGRB is to operate in the normal way, or

TGRB and TGRD are to be used together for buffer

operation.

0: TGRB operates normally

1: TGRB and TGRD used together for buffer operation*

BFA

R/W

Buffer Operation A

Specifies whether TGRA is to operate in the normal way, or

TGRA and TGRC are to be used together for buffer

operation.

0: TGRA operates normally

1: TGRA and TGRC used together for buffer operation



Reserved

This bit is always read as 0 and cannot be modified.

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