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SH7721 Datasheet(PDF) 570 Page - Renesas Technology Corp

Part # SH7721
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  1524 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7721 Datasheet(HTML) 570 Page - Renesas Technology Corp

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Section 14 Timer Unit (TMU)
Rev. 3.00 Jan. 18, 2008 Page 508 of 1458
REJ09B0033-0300
14.4
Interrupts
There is one source of TMU interrupts: underflow interrupts (TUNI).
14.4.1
Status Flag Set Timing
The UNF bit is set to 1 when TCNT underflows. Figure 14.6 shows the timing.
P
φ
TCNT
Underflow
signal
UNF
TUNI
(TCOR value)
H'00000000
Figure 14.6 UNF Set Timing
14.4.2
Status Flag Clear Timing
The status flag can be cleared by writing 0 from the CPU. Figure 14.7 shows the timing.
P
φ
Peripheral address bus
UNF, ICPF
TCR address
T1
T2
TCR write cycle
T3
Figure 14.7 Status Flag Clear Timing



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