SH7721 datasheet(566/1524 Pages) RENESAS

566 / 1524 page

Section 14 Timer Unit (TMU)

Rev. 3.00 Jan. 18, 2008 Page 504 of 1458

REJ09B0033-0300

Bit

Bit Name

Initial

Value

R/W

Description

4, 3

—

All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

TPSC2

TPSC1

TPSC0

R/W

Timer Prescaler 2 to 0

Select the TCNT count clock.

000: Count on P

φ/4

001: Count on P

φ/16

010: Count on P

φ/64

011: Count on P

φ/256

101: Count on RTC output clock (16 kHz)

Others are setting prohibited.

Note:

Only 0 can be written to clear the flag.

14.2.3

Timer Constant Registers (TCOR)

TCOR set the value to be set in TCNT when TCNT underflows.

TCOR are 32-bit readable/writable registers.

TCOR are initialized to H'FFFFFFFF at a power-on reset or manual reset. They are retained in

standby or sleep mode.

14.2.4

Timer Counters (TCNT)

TCNT count down upon input of a clock. The clock input is selected using the TPSC2 to TPSC0

bits in the timer control register (TCR).

When a TCNT count-down results in an underflow (H'00000000

→ H'FFFFFFFF), the underflow

flag (UNF) in the timer control register (TCR) of the relevant channel is set. The TCOR value is

simultaneously set in TCNT itself and the count-down continues from that value.

TCNT are initialized to H'FFFFFFFF at a power-on reset or manual reset. They are retained in

standby or sleep mode.

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