SH7721 datasheet(567/1524 Pages) RENESAS

567 / 1524 page

Section 14 Timer Unit (TMU)

Rev. 3.00 Jan. 18, 2008 Page 505 of 1458

REJ09B0033-0300

14.3

Operation

Each of the three channels has a 32-bit timer counter (TCNT) and a 32-bit timer constant register

(TCOR). TCNT counts down. The auto-reload function enables synchronized counting.

14.3.1

Counter Operation

When the STR0 to STR2 bits in the timer start register (TSTR) are set to 1, the corresponding

timer counter (TCNT) starts counting. When TCNT underflows, the UNF flag in the

corresponding timer control register (TCR) is set. At this time, if the UNIE bit in TCR is 1, an

interrupt request is sent to the CPU. Also at this time, the value is copied from TCOR to TCNT

and the down-count operation is continued.

(1)

Count Operation Setting Procedure

An example of the procedure for setting the count operation is shown in figure 14.2.

Select operation

Select counter

clock

Set interrupt generation

Set timer constant

Initialize timer

counter

Start counting

(1)

(2)

(3)

(4)

(5)

Note:

When an interrupt has been generated, clear the flag in the interrupt handler that caused it.

If interrupts are enabled without clearing the flag, another interrupt will be generated.

(1) Select the counter clock with the

bits TPSC2 to TPSC0 in the

timer control register (TCR).

(2) Use the UNIE bit in TCR to set

whether to generate an interrupt

when TCNT underflows.

(3) Set a value in the timer constant

set value plus 1).

(4) Set the initial value in the timer

counter (TCNT).

(5) Set the STR bit in the timer start

counting.

Figure 14.2 Setting Count Operation

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