SH7721 datasheet(601/1524 Pages) RENESAS

601 / 1524 page

Section 15

16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Jan. 18, 2008 Page 539 of 1458

REJ09B0033-0300

15.4.5

Phase Counting Mode

In phase counting mode, the phase difference between two external clock inputs is detected and

TCNT is incremented/decremented accordingly. This mode can be set for channels 2, and 3.

When phase counting mode is set, an external clock is selected as the counter input clock and

TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits

CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of

TIOR, TIER, and TGR are valid, and compare match and interrupt functions can be used.

The previous set value (initial output value set before the timer was started in phase counting

mode) is output from the TPU_TO pin in TIOR.

When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow

occurs while TCNT is counting down, the TCFU flag is set.

The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of

whether TCNT is counting up or down.

Table 15.7 shows the correspondence between external clock pins and channels.

Table 15.7

Phase Counting Mode Clock Input Pins

External Clock Pins

Channels

A-Phase

B-Phase

When channel 2 is set to phase counting mode

TPU_TI2A

TPU_TI2B

When channel 3 is set to phase counting mode

TPU_TI3A

TPU_TI3B

SH7721 Datasheet(PDF) 601 Page - Renesas Technology Corp