SH7721 datasheet(597/1524 Pages) RENESAS

597 / 1524 page

Section 15

16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Jan. 18, 2008 Page 535 of 1458

REJ09B0033-0300

(1)

Example of Buffer Operation Setting Procedure

Figure 15.9 shows an example of the buffer operation setting procedure.

Set buffer operation

Buffer operation

Set rewriting timing

Start count

[1]

[2]

Set external pin function

[3]

[4]

[1] Designate TGR for buffer operation with bits

BFA and BFB in TMDR.

[2] Set rewriting timing from the buffer register with

bit BFWT in TMDR.

[3] Set the external pin function in pin function

controller (PFC).

[4] Set the CST bit in TSTR to 1 to start the count

operation.

Figure 15.9

Example of Buffer Operation Setting Procedure

(2)

Example of Buffer Operation

Figure 15.10 shows an operation example in which PWM mode has been designated for channel 0,

and buffer operation has been designated for TGRA and TGRC. The settings used in this example

are TCNT clearing by compare match B, 1 output at compare match A (TPU_TO pin), and 0

output at counter clearing. Rewriting timing from the buffer register is set at counter clearing.

As buffer operation has been set, when compare match A occurs the output changes. When

counter clearing occurs by TGRB, the output changes and the value in buffer register TGRC is

simultaneously transferred to timer general register TGRA. This operation is repeated each time

compare match A occurs.

For details of PWM modes, see section 15.4.4, PWM Modes.

SH7721 Datasheet(PDF) 597 Page - Renesas Technology Corp