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SH7721 Datasheet(PDF) 844 Page - Renesas Technology Corp

Part # SH7721
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
PDF  1524 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7721 Datasheet(HTML) 844 Page - Renesas Technology Corp

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Section 24
USB Host Controller (USBH)
Rev. 3.00 Jan. 18, 2008 Page 782 of 1458
REJ09B0033-0300
Bit
Bit Name
Initial
Value
R/W
Description
31
FIT
0
R/W
Frame Interval Toggle
This bit is toggled by HCD whenever it loads a new value
into FrameInterval.
30 to 16 FSMPS14 to
FSMPS0
All 0
R/W
FS Largest Data Packet
This field specifies a value, which is loaded into the
Largest Data Packet Counter at the beginning of each
frame.
The counter value expresses the largest data amount of
the bit that can be transmitted and received in one
transaction by the host controller at any given time without
causing scheduling overrun. The field value is calculated
by HCD.
15, 14
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FI13
FI12
FI11
FI10
FI9
FI8
FI7
FI6
FI5
FI4
FI3
FI2
FI1
FI0
1
0
1
1
1
0
1
1
0
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Frame Interval
These bits specify the interval between two serial SOFs
with bit times. The nominal value is set to 11999. HCD
must store the current value of this field before resetting
the host controller. With this procedure, this bit is reset to
its nominal value by the host controller by setting the HCR
bit in USBHCS. HCD can select to restore the stored value
at the completion of the reset sequence.



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