SH7721 datasheet(841/1524 Pages) RENESAS

841 / 1524 page

Section 24

USB Host Controller (USBH)

Rev. 3.00 Jan. 18, 2008 Page 779 of 1458

REJ09B0033-0300

24.3.7

HCCA Register (USBHHCCA)

USBHHCCA includes physical addresses of the host controller communication area. The host

controller driver determines the alignment limitation by writing 1 to all bits in USBHHCCA and

by reading the content of USBHHCCA. Alignment is evaluated by checking the number of 0 in

the lower bits. The minimum alignment is 256 bytes. Consequently, bits 0 to 7 must be always

returned to 0 when they are read. This area is used to retain the control structure and interrupt table

that are accessed by the host controller and host controller driver.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 8

HCCA23 to

HCCA0

All 0

R/W

HCCA

Physical addresses of the host controller communication

area

7 to 0



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

24.3.8

Hc Period Current ED Register (USBHPCED)

USBHPCED includes a physical address of current Isochronous ED or Interrupt ED.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 4

PCED27 to

PCED0

All 0

PCED

Physical address of current Isochronous ED or Interrupt

3 to 0



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

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