SH7721 datasheet(972/1524 Pages) RENESAS

972 / 1524 page

Section 26

LCD Controller (LCDC)

Rev. 3.00 Jan. 18, 2008 Page 910 of 1458

REJ09B0033-0300

26.4.5

Setting the Display Resolution

The display resolution is set up in LDHCNR, LDHSYNR, LDVDLNR, LDVTLNR, and

LDVSYNR. The LCD current-alternating period for an STN or DSTN display is set by using the

LDACLNR. The initial values in these registers are typical settings for VGA (640

× 480 dots) on

an STN or DSTN display.

The clock to be used is set with the LDICKR. The LCD module frame rate is determined by the

display interval + retrace line interval (non-display interval) for one screen set in a size related

This LCDC has a Vsync interrupt function so that it is possible to issue an interrupt at the

beginning of each vertical retrace line period (to be exact, at the beginning of the line after the last

line of the display). This function is set up by using the LDINTR.

26.4.6

Power Management Registers

An LCD module normally requires a specific sequence for processing to do with the cutoff of the

input power supply. Settings in LDPMMR, LDPSPR, and LDCNTR, in conjunction with the LCD

power-supply control pins (LCD_VCPWC, LCD_VEPWC, and LCD_DON), are used to provide

processing of power-supply control sequences that suits the requirements of the LCD module.

Figures 26.4 to 26.7 are summary timing charts for power-supply control sequences and table 26.5

is a summary of available power-supply control sequence periods.

SH7721 Datasheet(PDF) 972 Page - Renesas Technology Corp