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SH7721 Datasheet(PDF) 1082 Page - Renesas Technology Corp |
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SH7721 Datasheet(HTML) 1082 Page - Renesas Technology Corp |
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1082 / 1524 page  Section 30 SIM Card Module (SIM) Rev. 3.00 Jan. 18, 2008 Page 1020 of 1458 REJ09B0033-0300 30.5 Usage Notes The following matters should be noted when using the smart card interface. (1) Receive Data Timing and Receive Margin When SCSMPL holds its initial value, the smart card interface operates at a basic clock frequency 372 times the transfer rate. During reception, the smart card interface samples the falling edge of the start bit using the serial clock for internal synchronization. Receive data is captured internally at the rising edge of the 186th serial clock pulse. This is shown in figure 30.7. 00 185 185 371 0 371 D0 D1 372 clock pulses 186 clock pulses Basic clock Received data Start bit Synchronization sampling timing Data sampling timing (RXD) Figure 30.7 Receive Data Sampling Timing in Smart Card Mode |
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