SH7721 datasheet(1092/1524 Pages) RENESAS

1092 / 1524 page

Section 31

MultiMediaCard Interface (MMCIF)

Rev. 3.00 Jan. 18, 2008 Page 1030 of 1458

REJ09B0033-0300

31.3

The MMCIF has the following registers. Refer to section 37, List of Registers, for more details on

the addresses and states of these registers in each operating mode.

• Mode register (MODER)

• Command type register (CMDTYR)

• Response type register (RSPTYR)

• Transfer byte number count register (TBCR)

• Transfer block number counter (TBNCR)

• Command registers 0 to 5 (CMDR0 to CMDR5)

• Response registers 0 to 16 (RSPR0 to RSPR16)

• Response register D (RSPRD)

• Command start register (CMDSTRT)

• Operation control register (OPCR)

• Command timeout control register (CTOCR)

• Data timeout register (DTOUTR)

• Card status register (CSTR)

• Interrupt control registers 0 and 1 (INTCR0 and INTCR1)

• Interrupt status registers 0 and 1 (INTSTR0 and INTSTR1)

• Pin mode control register (IOMCR)

• Transfer clock control register (CLKON)

• VDD/open drain control register (VDCNT)

• Data register (DR)

• FIFO pointer clear register (FIFOCLR)

• DMA control register (DMACR)

• Interrupt control register 2 (INTCR2)

• Interrupt status register 2 (INTSTR2)

SH7721 Datasheet(PDF) 1092 Page - Renesas Technology Corp