SH7721 datasheet(266/1524 Pages) RENESAS

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Section 5 Cache

Rev. 3.00 Jan. 18, 2008 Page 204 of 1458

REJ09B0033-0300

Table 5.6

LRU and Way Replacement (when W2LOCK = 0 and W3LOCK =1)

LRU (Bits 5 to 0)

Way to be Replaced

000000, 000001, 000011, 001011, 100000, 100001, 101001, 101011

000100, 000110, 000111, 001111, 010100, 010110, 011110, 011111

110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111

Table 5.7

LRU and Way Replacement (when W2LOCK = 1 and W3LOCK =1)

LRU (Bits 5 to 0)

Way to be Replaced

000000, 000001, 000011, 000100, 000110, 000111, 001011, 001111,

010100, 010110, 011110, 011111

100000, 100001, 101001, 101011, 110000, 110100, 111000, 111001,

111011, 111100, 111110, 111111

5.2.3

Cache Control Register 3 (CCR3)

The CCR3 register controls the cache size to be used. The cache size must be specified according

to the LSI to be selected. If the specified cache size exceeds the size of cache incorporated in the

LSI, correct operation cannot be guaranteed. Note that programs that change the contents of the

CCR3 register should be placed in un-cached address space. In addition, note that all cache entries

must be invalidated by setting the CF bit in the CCR1 to 1 before accessing the cache after the

CCR3 is modified.

Bit

Bit Name

Initial

Value

R/W

Description

31 to 24



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

23 to 16

CSIZE7 to

CSIZE0

H'01

R/W

Cache Size

Specify the cache size as shown below.

0000 0001: 16-kbyte cache

0000 0010: 32-kbyte cache

Settings other than above are prohibited.

15 to 0



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

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