SH7721 datasheet(265/1524 Pages) RENESAS

265 / 1524 page

Section 5 Cache

Rev. 3.00 Jan. 18, 2008 Page 203 of 1458

REJ09B0033-0300

Table 5.3

Way Replacement when a PREF Instruction Misses the Cache

DSP Bit

W3LOAD

W3LOCK

W2LOAD

W2LOCK

Way to be Replaced

Determined by LRU (table 5.2)

Determined by LRU (table 5.5)

Determined by LRU (table 5.6)

Determined by LRU (table 5.7)

Way 2

Way 3

Note:

Don’t care

W3LOAD and W2LOAD should not be set to 1 at the same time.

Table 5.4

Way Replacement when Instructions other than the PREF Instruction Miss the

Cache

DSP Bit

W3LOAD

W3LOCK

W2LOAD

W2LOCK

Way to be Replaced

Determined by LRU (table 5.2)

Determined by LRU (table 5.5)

Determined by LRU (table 5.6)

Determined by LRU (table 5.7)

Note:

Don’t care

W3LOAD and W2LOAD should not be set to 1 at the same time.

Table 5.5

LRU and Way Replacement (when W2LOCK = 1 and W3LOCK =0)

LRU (Bits 5 to 0)

Way to be Replaced

000000, 000001, 000100, 010100, 100000, 100001, 110000, 110100

000011, 000110, 000111, 001011, 001111, 010110, 011110, 011111

101001, 101011, 111000, 111001, 111011, 111100, 111110, 111111

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