SH7721 datasheet(263/1524 Pages) RENESAS

263 / 1524 page

Section 5 Cache

Rev. 3.00 Jan. 18, 2008 Page 201 of 1458

REJ09B0033-0300

5.2.2

Cache Control Register 2 (CCR2)

The CCR2 register controls the cache locking mechanism in cache lock mode only. The CPU

enters the cache lock mode when the DSP bit (bit 12) in the status register (SR) is set to 1 or the

lock enable bit (bit 16) in the cache control register 2 (CCR2) is set to 1. The cache locking

mechanism is disabled in non-cache lock mode (DSP bit = 0).

When a prefetch instruction (PREF@Rn) is issued in cache lock mode and a cache miss occurs,

the line of data pointed to by Rn will be loaded into the cache, according to the setting of bits 9

and 8 (W3LOAD, W3LOCK) and bits 1 and 0 (W2LOAD, W2LOCK in CCR2).

Table 5.3 shows the relationship between the settings of bits and the way that is to be replaced

when the cache is missed by a prefetch instruction.

On the other hand, when the cache is hit by a prefetch instruction, new data is not loaded into the

cache and the valid entry is held. For example, a prefetch instruction is issued while bits

W3LOAD and W3LOCK are set to 1 and the line of data to which Rn points is already in way 0,

the cache is hit and new data is not loaded into way 3.

In cache lock mode, bits W3LOCK and W2LOCK restrict the way that is to be replaced, when

instructions other than the prefetch instruction are issued. Table 5.4 shows the relationship

between the settings of bits in CCR2 and the way that is to be replaced when the cache is missed

by instructions other than the prefetch instruction.

Programs that change the contents of the CCR2 register should be placed in address space that is

not cached.

SH7721 Datasheet(PDF) 263 Page - Renesas Technology Corp