SH7721 datasheet(260/1524 Pages) RENESAS

260 / 1524 page

Section 5 Cache

Rev. 3.00 Jan. 18, 2008 Page 198 of 1458

REJ09B0033-0300

Figure 5.1 shows the cache structure.

24 (1 + 1 + 22) bits

128 (32

× 4) bits

6 bits

LW0 to LW3: Longword data 0 to 3

Entry 0

Entry 1

Entry 255

255

V U Tag address

LW0

LW1

LW2

LW3

Address array (ways 0 to 3)

Data array (ways 0 to 3)

LRU

Figure 5.1 Cache Structure

(1)

Address Array

The V bit indicates whether the entry data is valid. When the V bit is 1, data is valid; when 0, data

is not valid. The U bit indicates whether the entry has been written to in write-back mode. When

the U bit is 1, the entry has been written to; when 0, it has not. The tag address holds the physical

address used in the external memory access. It is composed of 22 bits (address bits 31 to 10) used

for comparison during cache searches.

In this LSI, the top three of 32 physical address bits are used as shadow bits (see section 9, Bus

State Controller (BSC)), and therefore the top three bits of the tag address are cleared to 0.

The V and U bits are initialized to 0 by a power-on reset, but are not initialized by a manual reset.

The tag address is not initialized by either a power-on or manual reset.

(2)

Data Array

Holds a 16-byte instruction or data. Entries are registered in the cache in line units (16 bytes). The

data array is not initialized by a power-on or manual reset.

SH7721 Datasheet(PDF) 260 Page - Renesas Technology Corp