SH7721 datasheet(272/1524 Pages) RENESAS

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Section 5 Cache

Rev. 3.00 Jan. 18, 2008 Page 210 of 1458

REJ09B0033-0300

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Address-Array Write (Associative Operation)

When writing with the associative bit (A bit) of the address = 1, the addresses in the four ways for

the entry specified by the address field of the write instruction are compared with the tag address

that is specified by the data field of the write instruction. If the MMU is enabled in this case, a

virtual address specified by data is translated into a physical address via the TLB before

comparison. Write the U bit and the V bit specified by the data field of the write instruction to the

entry of the way that has a hit. However, the tag address and LRU bits remain unchanged. When

there is no way that receives a hit, nothing is written and there is no operation. This function is

used to invalidate a specific entry in the cache. When the U bit of the entry that has received a hit

is 1 at this point, writing back should be performed. However, when 0 is written to the V bit, 0

must also be written to the U bit of that entry.

5.4.2

Data Array

The data array is mapped onto H'F1000000 to H'F1FFFFFF. To access a data array, the 32-bit

address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified.

The address field specifies information for selecting the entry to be accessed; the data field

specifies the longword data to be written to the data array.

In the address field, specify the entry address for selecting the entry, L for indicating the longword

position within the (16-byte) line, W for selecting the way, and H'F1 for indicating data array

access. As for L, B'00 indicates longword 0, B'01 indicates longword 1, B'10 indicates longword

2, and B'11 indicates longword 3. As for W, B'00 indicates way 0, B

′01 indicates way 1, B'10

indicates way 2, and B

′11 indicates way 3.

Since access size of the data array is fixed at longword, bits 1 and 0 of the address field should be

set to B'00.

Figure 5.4 shows the address and data formats in 16-kbyte mode. For other cache size modes,

change the entry address and W as shown in table 5.8.

The following two operations on the data array are available. The information in the address array

is not affected by these operations.

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Data-Array Read

Read the data specified by L of the address filed, from the entry that corresponds to the entry

address and the way that is specified by the address filed.

SH7721 Datasheet(PDF) 272 Page - Renesas Technology Corp