SH7721 datasheet(273/1524 Pages) RENESAS

Part #	SH7721

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

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Manufacturer	RENESAS [Renesas Technology Corp]

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Section 5 Cache

Rev. 3.00 Jan. 18, 2008 Page 211 of 1458

REJ09B0033-0300

(2)

Data-Array Write

Write the longword data specified by the data filed, to the position specified by L of the address

field, in the entry that corresponds to the entry address and the way specified by the address field.

(1) Address array access

(a) Address specification

Read access

Write access

(b) Data specification (both read and write accesses)

(2) Data array access (both read and write accesses)

(a) Address specification

1111 0000

*--------*

Entry address

1111 0000

*--------*

Entry address

LRU

Tag address (31 to 10)

1111 0001

*--------*

Entry address

(b) Data specification

Longword

*: Don’t care bit

X: 0 for read, don’t care for write

Figure 5.4 Specifying Address and Data for Memory-Mapped Cache Access

(16-kbyte mode)

Table 5.8

Address Format Based on the Size of Cache to be Assigned to Memory

Cache Size

Entry Address Bits

W Bit

16 kbytes

11 to 4

13 and 12

32 kbytes

12 to 4

14 to 13

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