7477 datasheet(103/354 Pages) RENESAS

103 / 354 page

7470/7471/7477/7478 GROUP USER’S MANUAL

1-86

HARDWARE

1.12 Timers

Fig. 1.12.14 Structure of Timer mode register 2

(4) Timer mode register 2 (TM2: Address 00FA16)

The Timer mode register 2 consists of bits that control a mode selection and a count source selection.

Figure 1.12.14 shows a structure of Timer mode register 2.

(5) Timer FF register (TF: Address 00F716)

The Timer FF register consists of bits that are used for initialization in the pulse output mode.

Figure 1.12.15 shows a structure of Timer FF register.

Fig. 1.12.15 Structure of Timer FF register

b7 b6 b5 b4 b3 b2 b1 b0

Name

Function

At reset R W

Timer mode register 2 (TM2) [Address

Timer 1 overflow FF

set enable bit

Timer mode register 2

Timer 4 overflow FF

set enable bit

Nothing is allocated for these bits. These are

write disabled bits and are undefined at reading.

Timer 3, timer 4 count

overflow signal selection bit

Timer 3, timer 4

function selection bit

0 : Set disable

1 : Set enable

0 : Set disable

1 : Set enable

0 : Timer 1 overflow

1 : Timer 2 overflow

0 : Ordinary mode

1 : PWM mode

?? !

00FA16]

b7 b6 b5 b4 b3 b2 b1 b0

Name

Function

Timer 1

division flip-flop

At reset R W

Timer FF register (TF) [Address

Timer FF register

Nothing is allocated for these bits. These are

write disabled bits and are undefined at

reading.

? !

Timer 4

division flip-flop

0 : Initial value is “0”

1 : Initial value is “1”

0 : Initial value is “0”

1 : Initial value is “1”

00F716]

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