7477 datasheet(109/354 Pages) RENESAS

109 / 354 page

HARDWARE

1-92

7470/7471/7477/7478 GROUP USER’S MANUAL

1.13 Serial I/O

2 Transmit operation of Serial I/O

The transmit operation of the Serial I/O is described below.

q Start of transmit operation

Transmit operation begins by writing transmit data into the Serial I/O register

V2 in the transmit

enable state.

V1 At the time when this data has been written, “7” is set in the Serial I/O counter

(address 00DE16, bit 4 – 6), so that the synchronous clock is forced to go to “H.”

V 1: State in which the register for transmit operation has been initialized. Refer to “[Transmit

setting method]” which will be described later.

V 2: When the external clock is selected, perform a write operation while the synchronous clock is

at “H.”

q Transmit operation

1The transmit data written in the Serial I/O register is output from the P15/SOUT pin in synchronization

with the fall of the synchronous clock. At this time, the Serial I/O counter is decremented by 1.

2Transmit data is output starting with the least significant bit of the Serial I/O register. Each time

one bit is output, the contents of the Serial I/O register are shifted by 1 in the direction of the

least significant bit.

3After the transmit shift operation is completed, an interrupt request occurs at the rise of the last

cycle of the synchronous clock, so that the Serial I/O interrupt request bit is set

V3 to “1.”

V 3: When the internal clock is selected as a synchronous clock, the shift clock supply to the Serial

I/O register is automatically stopped after 8-bit data is transmitted (the Serial I/O counter

overflows). When the external clock is selected, the contents of the Serial I/O register are

continuously sifted while the synchronous clock is input. Accordingly, stop it externally.

__________

When using the SRDY output

__________

At the time when transmit data has been written, the level of the SRDY signal changes from “H” to

“L” and the level of the SARDY signal changes from “L” to “H,” by which a receive ready state can

__________

be known externally. The SRDY signal goes to “H” at the first fall of the synchronous clock and the

SARDY

signal goes to “L” at the rise of the last cycle of the synchronous clock.

Figure 1.13A.2 shows a transmit operation and Figure 1.13A.3 shows a transmit timing chart.

7477 Datasheet(PDF) 109 Page - Renesas Technology Corp