7477 datasheet(114/354 Pages) RENESAS

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HARDWARE

1-97

7470/7471/7477/7478 GROUP USER’S MANUAL

1.13 Serial I/O

[Receive setting method]

1Clear the Serial I/O interrupt enable bit (bit 6 of the Interrupt control register 1) to “0.”

2Clear the Port P14 direction register to “0” to set it to the input mode.

3Clear the Serial I/O mode register according to “Table 1.13A.2.”

4When using the Serial I/O interrupt,

[1] Clear the Serial I/O interrupt request bit (bit 6 of the Interrupt request register 1) to “0.”

[2] Set the Serial I/O interrupt enable bit to “1.”

5Write the following data into the Serial I/O register.

•

Transmit data in the full-duplex data communication

•

Arbitrary dummy data in the half-duplex data communication

Note: When the external clock is selected, write data into the Serial I/O register while the synchronous

clock is at “H.”

Table 1.13A.2 shows a Serial I/O receive setting.

Table 1.13A.2 Serial I/O receive setting

Serial I/O mode register

(SM: Address 00DC16)

Bit

Setting value

External clock

Internal clock

Ordinary port (P15, P16) (Note 2)

Serial I/O port (SOUT, CLK) (Note 3)

Ordinary port

__________

SRDY

signal output

__________

SRDY

signal

SARDY signal

Ordinary mode

Byte specification mode

CMOS output

N channel open drain output

Item

Synchronous clock selection

__________

P15/SOUT, SRDY pin output

format

(Note 4, Note 5)

Serial I/O

Byte specification mode selection

Serial I/O port using

_______________

SRDY

signal output selection

__________

SRDY

signal selection

Notes 1: Select the internal clock as a synchronous clock in the following condition. In the 7470 group,

however, f(XCIN) is not available.

q When a divided signal of f(XIN) is selected, the system clock is f(XIN).

q When a divided signal of f(XCIN) is selected, the system clock is f(XCIN).

Select a system clock state by bit 7 of the CPU mode register.

2: When the external clock is selected, the P16/CLK pin becomes clock input pin CLK regardless

of the set value of bit 3 of the Serial I/O mode register. For this reason, only P1 5 is available

as an ordinary port.

3: When the ordinary port is switched over to the Serial I/O port, the Serial I/O interrupt request bit

may be set to “1.” Clear the Serial I/O interrupt request bit to “0” after one instruction or more

after switching the ordinary port over to the Serial I/O port.

4: When ordinary P17 is selected by bit 4 of the Serial I/O mode register, the CMOS output is

provided regardless of the set value of bit 7.

5: When SOUT is selected by bit 3 of the Serial I/O mode register, the data written in the Serial

I/O register is output from the SOUT pin in synchronization with the fall of the synchronous clock.

Synchronous clock (at internal

clock selection)

(Note 1)

f(XIN)/8

f(XCIN)/8

f(XIN)/16

f(XCIN)/16

f(XIN)/32

f(XCIN)/32

f(XIN)/512

f(XCIN)/512

b1 • b0

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