7477 datasheet(118/354 Pages) RENESAS

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HARDWARE

1-101

7470/7471/7477/7478 GROUP USER’S MANUAL

1.13 Serial I/O

1.13A.3 Pins

The 7470/7471 group uses 4 pins for data transmit, data receive, shift clock transmit/receive and receive

ready signal output. All these pins are used in common with P1. A function selection is made by the Serial

_______________

I/O port selection bit (bit 3) and the SRDY signal output selection bit (bit 4) of the Serial I/O mode register

(SM : Address 00DC16).

The function of each pin is explained below.

(1) Data transmit pin [SOUT]

Transmit data is output bit by bit. This pin is used in common with P15. When the Serial I/O port

selection bit (bit 3) of the Serial I/O mode register is set to “1,” this pin becomes a Serial I/O data

output pin.

(2) Data receive pin [SIN]

Data is input bit by bit. This pin is used in common with P14. When the port P14 direction register

is put into the input mode, this pin becomes a Serial I/O data input pin.

(3) Shift clock transmit/receive pin [CLK]

This pin inputs (receives from the outside) or outputs (supplies to the outside) the shift clock for data

transmit/receive. This pin is used in common with P16.

The internal clock or the external clock can be selected by bit 2 of the Serial I/O mode register.

__________

(4) Receive enable signal output pins [SRDY], [SARDY]

This pin informs the outside of a receive ready state. This pin is used in common with P17.

____________

SRDY

signal

•

__________

SRDY

signal output selection bit (bit 4) of Serial I/O mode register is set to “1.”

•

__________

SRDY

signal selection bit (bit 5) of Serial I/O mode register is cleared to “0.”

When the above 2 conditions are satisfied, the level of the pin changes from “H” to “L” at the timing

at which data is written into the Serial I/O register, informing the outside of a receive ready state.

q SARDY signal

•

__________

SRDY

signal output selection bit (bit 4) of Serial I/O mode register is set to “1.”

•

__________

SRDY

signal selection bit (bit 5) of Serial I/O mode register is set to “1.”

When the above 2 conditions are satisfied, the level of the pin changes from “L” to “H” at the timing

at which data is written into the Serial I/O register, informing the outside of a receive ready state.

1.13A.4 Notes on use

When the external clock is selected, take the following points into consideration.

1When writing data into the Serial I/O register, perform a write operation while the synchronous clock

is at “H.”

2The shift operation of the Serial I/O register is continued while the synchronous clock is input to the

Serial I/O circuit. When the external clock is selected, stop the synchronous clock at the end of 8

cycles. (When the internal clock is selected, the synchronous clock stops automatically at the end of

8 cycles.)

3Set the “H” and “L” widths (TWH, TWL) of the pulse used as the external clock source to TWH, TWL [s]

> 2/(system clock frequency [Hz]). For example, when the system clock is 8 MHz, use a clock of 2

MHz or less (duty ratio 50 %).

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