7477 datasheet(276/354 Pages) RENESAS

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7470/7471/7477/7478 GROUP USER’S MANUAL

APPLICATION

2.8 Low-power dissipation function

7470

7471

7477

7478

2.8 Low-power dissipation function

2.8.1 CPU mode register

The CPU mode register consists of a stack page selection bit+1 and internal system clock control

bits+2.

+1: In the products having a RAM capacity of 192 bytes or less, a RAM is not arranged on page 1,

so this bit is not available. (Be sure to set this bit to “0.”)

+2: In the 7470/7477 group, which is not provided with a sub-clock (f(XCIN)) generating circuit, f(XCIN)

is not used. (Be sure to set this bit to “0.”)

Figure 2.8.1 shows a structure of CPU mode register.

Fig. 2.8.1 Structure of CPU mode register

b7 b6 b5 b4 b3 b2 b1 b0

CPU mode register (CPUM) [Address

At reset R W

CPU mode register

0, 1

? !

Name

Function

Fix these bits to “0.”

Nothing is allocated for this bit. This is write

enabled bit and is undefined at reading.

Main clock (XIN–XOUT)

stop bit

XCOUT drive capacity

selection bit

Stack page selection

bit

Internal system clock

selection bit

0: In page 0 area

1: In page 1 area

(Note 1)

0: Low

1: High

(Note 2)

0: Oscillates

1: Stops

(Note 2)

0: XIN–XOUT selected

(Ordinary mode)

1: XCIN–XCOUT selected

(Low speed mode)

(Note 2)

P50, P51/XCIN,XCOUT

selection bit

0: P50, P51

1: XCIN, XCOUT (Note 2)

Notes 1:

In the products having a RAM capacity of 192 bytes or

less, set this bit to “0.”

Since the 7470/7477 group is not provided with the

sub-clock generating circuit, f(X

Fix these bits to “0.”

00FB16]

CIN

) cannot be used.

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