7477 datasheet(301/354 Pages) RENESAS

301 / 354 page

3-7

7470/7471/7477/7478 GROUP USER’S MANUAL

APPENDIX

3.1 Control registers

Fig. 3.1.12 Structure of Serial I/O status register

Fig. 3.1.11 Structure of Transmit/receive buffer register

b7 b6 b5 b4 b3 b2 b1 b0

Transmit/receive buffer register (TB/RB) [Address

Function

At reset R W

Transmit/receive buffer register (7477/7478 group)

A value of “0016” to “FF16” can be

set as transmit data.

The transmit data is transferred

automatically by writing the transmit

data into the Transmit shift register.

When all receive data has been input

into the Receive shift register, the

receive data is automatically trans-

ferred to the receive buffer register.

At transmit:

At receive:

00E016]

b7 b6 b5 b4 b3 b2 b1 b0

Serial I/O status register (SIOSTS) [Address

At reset

R W

Serial I/O status register (7477/7478 group)

Name

Function

Transmit buffer

empty flag (TBE)

0 : Buffer full

1 : Buffer empty

Receive buffer full

flag (RBF)

0 : Buffer empty

1 : Buffer full

Transmit shift

completion flag (TSC)

0 : Transmit shift in progress

1 : Transmit shift completed

Overrun error flag

(OE)

0 : No error

1 : Overrun error

Parity error flag

(PE)

0 : No error

1 : Parity error

Framing error flag

(FE)

0 : No error

1 : Framing error

Nothing is allocated for this bit. This is a write

disabled bit. When this bit is read out, the value

is “1.”

Summing error

flag (SE)

0 : (OE) U (PE) U (FE) = 0

1 : (OE) U (PE) U (FE) = 1

00E116]

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