7477 datasheet(305/354 Pages) RENESAS

305 / 354 page

3-11

7470/7471/7477/7478 GROUP USER’S MANUAL

APPENDIX

3.1 Control registers

Fig. 3.1.20 Structure of CPU mode register

Fig. 3.1.19 Structure of Timer mode register 2

b7 b6 b5 b4 b3 b2 b1 b0

Name

Function

At reset R W

Timer mode register 2 (TM2) [Address

Timer 1 overflow FF

set enable bit

Timer mode register 2

Timer 4 overflow FF

set enable bit

Nothing is allocated for these bits. These are

write disabled bits and are undefined at reading.

Timer 3, timer 4 count

overflow signal selection bit

Timer 3, timer 4

function selection bit

0 : Set disable

1 : Set enable

0 : Set disable

1 : Set enable

0 : Timer 1 overflow

1 : Timer 2 overflow

0 : Ordinary mode

1 : PWM mode

?? !

00FA16]

b7 b6 b5 b4 b3 b2 b1 b0

CPU mode register (CPUM) [Address

At reset R W

CPU mode register

0, 1

? !

Name

Function

Fix these bits to “0.”

Nothing is allocated for this bit. This is write

enabled bit and is undefined at reading.

Main clock (XIN–XOUT)

stop bit

XCOUT drive capacity

selection bit

Stack page selection

bit

Internal system clock

selection bit

0: In page 0 area

1: In page 1 area

(Note 1)

0: Low

1: High

(Note 2)

0: Oscillates

1: Stops

(Note 2)

0: XIN–XOUT selected

(Ordinary mode)

1: XCIN–XCOUT selected

(Low speed mode)

(Note 2)

P50, P51/XCIN,XCOUT

selection bit

0: P50, P51

1: XCIN, XCOUT (Note 2)

Notes 1:

In the products having a RAM capacity of 192 bytes or

less, set this bit to “0.”

Since the 7470/7477 group is not provided with the

sub-clock generating circuit, f(X

Fix these bits to “0.”

00FB16]

CIN

) cannot be used.

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