33937 datasheet(28/47 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33937

FUNCTIONAL INTERNAL BLOCK DESCRIPTION

In order to achieve a 100% duty cycle operation of the High

Side external FETs, a fully integrated trickle charge pump

provides the charge necessary to maintain the external FET

gates at fully enhanced levels. The trickle charge pump has

limited ability to supply external leakage paths while

performing it’s primary function. The graphs in Figures 11

through 14 beginning on page 20 show the typical margin for

supplying external current loads. These limits are based on

maintaining the voltage at CBOOT at least 3.0 V greater than

the voltage on the HS_S for that phase. If this voltage

differential becomes less than 3.0 V, the corresponding high

side FET will most likely not remain fully enhanced and the

high side driver may malfunction due to insufficient bias

voltage between CBOOT and HS_S.

The slew rate of the external output FET is limited by the

driver output impedance, overall (external and internal) gate

resistance and the load capacitance. To ensure the Low Side

FET is not turned on by a large positive dV/dt on the drain of

the Low Side FET, the turn-on slew rate of the High Side

should be limited. If the slew rate of the High Side is limited

by the gate-drain capacitance of the High Side FET, then the

displacement current injected into the Low Side gate drive

output will be approximately the same value. Therefore, to

ensure the Low Side drivers can be held off, the voltage drop

across the Low Side gate driver must be lower than the

threshold voltage of the Low Side FET (see Figure 17).

Similarly, during large negative dV/dt, the High Side FET

will be able to remain off if its gate drive Low Side switch,

develops a voltage drop less than the threshold voltage of the

High Side FET. The gate drive Low Side switch discharges

the gate to the source.

Additionally, during negative dV/dt the Low Side gate drive

could be forced below ground. The Low Side FETs must not

inject detrimental substrate currents in this condition.

The occurrence of these cases depends on the polarity of

the load current during switching.

Figure 17. Positive DV/dt Transient

DRIVER FAULT PROTECTION

The 33937 IC integrates several protection mechanisms

against various faults. The first of them is the Current Sense

Amplifier with the Over-current Comparator. These two

blocks are common for all three driver phases.

Current Sense Amplifier

This amplifier is usually connected as a differential

amplifier (see Figure 9). It senses a current flowing through

the external FETs as a voltage across the current sense

resistor RSENSE. Since the amplifier common mode range

does not extend below ground, it is necessary to use an

external reference to permit measuring both positive and

negative currents.

The amplifier output can be monitored directly (e.g. by the

microcontroller’s ADC) at the AMP_OUT pin, providing the

means for closed loop control with the 33937.

The output voltage is internally compared with the Over-

current Comparator threshold voltage (see Figure 22).

Over-current Comparator

The amplified voltage across RSENSE is compared with the

pre-set threshold value by the over-current comparator input.

If the Current Sense Amplifier output voltage exceeds the

threshold of the Over-current Comparator it would change

the status of its output (OC_OUT pin) and the fault condition

would be latched (see Figure 20).

The occurrence of this fault would be signalled by the

return value of the Status Register 0. If the proper Interrupt

Mask has been set, this fault condition will generate an

Phase x

Output

Phase

Return

Px_LS_S

Px_LS_G

Px_HS_S

Low

-Side

Driver

Control

Px_LS_G

Px_HS_G

Deadtime

-VD

VSUP

Phase x Output Voltage

dV/dt

CGS

CDG

CDS

iCDG

VLS

33927

Discrete

FET

Package

33937 Datasheet(PDF) 28 Page - Freescale Semiconductor, Inc

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