Analog Integrated Circuit Device Data

16

Freescale Semiconductor

33937

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

SPI INTERFACE TIMING

Maximum Frequency of SPI Operation

–

4.0

MHz

Internal Time Base

13

17

25

MHz

Internal Time Base drift from value at 25

°C (50)

-5.0

–

5.0

%

Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (50)

100

–

–

ns

Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (50)

100

–

–

ns

SI to Falling Edge of SCLK (Required Setup Time) (50)

25

–

–

ns

Falling Edge of SCLK to SI (Required Setup Time) (50)

25

–

–

ns

SI, CS, SCLK Signal Rise Time (50), (51)

–

5.0

–

ns

SI, CS, SCLK Signal Fall Time (50), (51)

–

5.0

–

ns

Time from Falling Edge of CS to SO Low-impedance (50), (52)

–

55

100

ns

Time from Rising Edge of CS to SO High-impedance (50), (53)

–

100

125

ns

Time from Rising Edge of SCLK to SO Data Valid (50), (54)

–

80

125

ns

Time from Rising Edge of CS to Falling Edge of the next CS (50)

200

–

–

ns

Notes

50.

This parameter is guaranteed by design, not production tested.

51.

Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.

52.

Time required for valid output status data to be available on SO pin.

53.

Time required for output states data to be terminated at SO pin.

54.

Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load.

Table 4. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 8.0 V

Characteristic

Symbol

Min

Typ

Max

Unit