SAF7115 datasheet(4/35 Pages) NXP

4 / 35 page

SAF7115_1

Product data sheet

Rev. 01 — 15 October 2008

4 of 35

NXP Semiconductors

SAF7115

Multistandard video decoder

2.5 Clock generation

I On-chip line locked clock generation according ITU-601

I Generation of a frame locked audio master clock to support a constant number of

audio clocks per video ﬁeld

I Second onboard analog Phase-Locked Loop (PLL) to be used for:

N On-chip line locked square pixel clock generation for PAL and NTSC square pixel

video output or

N The generation of a low jitter frame locked audio clock from the audio master clock

through reuse of the analog square pixel PLL. The audio clock frequencies

supported are 256

× f

s, 384 × fs and 512 × fs (fs = 32 kHz, 44.1 kHz or 48 kHz)

2.6 General features

I CMOS 3.3 V device with 5 V tolerant digital inputs and I/O ports

I Programming through serial I2C-bus, full read-back ability by an external controller,

bit-rate up to 400 kbit/s

I Software controlled power saving stand-by modes

I Boundary Scan Test circuit complies to the IEEE Std. 1149.b1-1994

Applications

I General industrial video applications

I In-car TV reception

I In-car entertainment

I In-car navigation platforms

Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

SAF7115HW

HTQFP100

plastic thermal enhanced thin quad ﬂat package; 100 leads; body

× 14 × 1 mm; exposed die pad

SOT638-1

SAF7115ET

TFBGA160

plastic thin ﬁne-pitch ball grid array package; 160 balls

SOT1016-1

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