SAF7115_1

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 01 — 15 October 2008

12 of 35

NXP Semiconductors

SAF7115

Multistandard video decoder

[1]

A = analog, I = input, O = output, P = power, st = strapping, pu = pull-up, pd = pull-down, od = open-drain.

[2]

For CGC1 and CGC2.

[3]

For analog inputs AI1x.

[4]

For analog inputs AI2x.

[5]

For normal operation connect pins AI1D and AI2D to ground through a capacitor. In principle both analog input stages can operate in

differential mode, too, depending on the application. This may be interesting for differential video (CVBS). Please contact NXP for more

information.

[6]

This contains information about actual system clock frequency, field rate, odd/even sequence, decoder status, subcarrier phase and

frequency and PAL sequence (according to RTC level 3.1, refer to external document

RTC Functional Specification for details), can be

strapped to supply through a 3.3 k

pull-down) to 40h and 41h.

[7]

According to the

IEEE1149.b1-1994 standard pins TDI and TMS are input pins with an internal pull-up transistor and TDO is a 3-state

output pin. Pins TCK and TRST_N are also built with internal pull-up.

[8]

This pin provides easy initialization of BST circuitry. Pin TRST_N can be used to force the Test Access Port (TAP) controller to the

test-logic-reset state (normal operation) at once.

XRDY

96

A4

O

task flag or read signal from scaler, controlled by bit XRQT

(subaddress 83h)

XRH

92

A6

I/O

horizontal reference I/O expansion-port: in 10-bit video output

mode: this signal represents the video bit 1

XRV

91

B6

I/O

vertical reference I/O expansion-port: in 10-bit video output mode:

this signal represents the video bit 0 (LSB)

XTRI

80

A12

I/pd

X-port output control signal, affects all X-port pins (XPD[7:0],

XRH, XRV, XDQ and XCLK) enable and active polarity is under

software control (bits XPE in subaddress 83h)

Host port (H-port)

HPD7

64

G13

I/O

MSB of host port data I/O, carries CbCr chrominance information

in 16-bit video I/O modes

HPD6

65

G14

I/O

MSB

− 1 of host port data I/O, carries CbCr chrominance

information in 16-bit video I/O modes

HPD5

66

F13

I/O

MSB

− 2 of host port data I/O, carries CbCr chrominance

information in 16-bit video I/O modes

HPD4

67

F14

I/O

MSB

− 3 of host port data I/O, carries CbCr chrominance

information in 16-bit video I/O modes

HPD3

69

E14

I/O

MSB

− 4 of host port data I/O, carries CbCr chrominance

information in 16-bit video I/O modes

HPD2

70

D13

I/O

MSB

− 5 of host port data I/O, carries CbCr chrominance

information in 16-bit video I/O modes

HPD1

71

D14

I/O

MSB

− 6 of host port data I/O, carries CbCr chrominance

information in 16-bit video I/O modes

HPD0

72

C13

I/O

LSB of host port data I/O, carries CbCr chrominance information

in 16-bit video I/O modes

Table 4.

Symbol

Pin

Description

HTQFP100

TFBGA160