SAF7115 datasheet(9/35 Pages) NXP

9 / 35 page

SAF7115_1

Product data sheet

Rev. 01 — 15 October 2008

9 of 35

NXP Semiconductors

SAF7115

Multistandard video decoder

Supplies (digital)

VDDD(IO)

1, 25, 51 and

A1, A14, P1

and P14

I/O digital supply voltage

VDDD(CORE)

33, 43, 58,

68, 83 and 93

B5, B10,

E13, K13, N5

and N10

core digital supply voltage

VSSD(CORE)

38, 63 and 88 A8, H14 and

core digital ground supply voltage

VSSD(IO)

26, 50, 76

and 100

D4 to D11,

E4 to E11,

F4 to F11,

G4 to G11,

H4 to H11,

J4 to J11,

K4 to K11

and L6 to L9

I/O digital ground supply voltage

Analog inputs

AGND

analog signal ground reference for all AIx inputs

AI21

analog input 21

AI22

analog input 22

AI23

analog input 23

AI24

analog input 24

AI2D

differential input for ADC channel 2 (pins AI24, AI23, AI22 and

AI21)[5]

AI11

analog input 11

AI12

analog input 12

AI1D

differential input for ADC channel 1 (pins AI12 and AI11)[5]

Analog output

AOUT

analog test output (do not connect)

I2C-bus

SCL

I (/O)/od

serial clock input (/output) with inactive output path

SDA

I (/O)/od

serial data input (/output)

General control

I/pu

chip enable or reset input (with internal pull-up)

RESO_N

reset output (active low)

Audio clock

ALRCLK

(I/) O/st/pd audio left/right clock output: can be strapped to supply through a

3.3 k

Ω resistor indicating that the default 24.576 MHz crystal

(internal pull-down) has been replaced by a 32.11 MHz crystal

AMCLK

audio master clock output

AMXCLK

audio master external clock input

ASCLK

audio serial clock output

Table 4.

Pin description …continued

Symbol

Type[1]

Description

HTQFP100

TFBGA160

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