2.1.4

SD/SDIO card: How to Handle SDIO interrupt

2.1.5

Peripherals: Electrostatic Discharge (ESD) Sensitivity Classification

Silicon Revision 1.1 Usage Notes and Known Design Exceptions to Functional Specifications

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For example, when the access size (ACCWD) is 4 bytes and the FIFO level (FIFOLEV=1) is 256-bits

or 32 bytes, and if the number of bytes in FIFO is

• 0 to 3: then, FIFOFUL=0, FIFOEMP=1

• 4 to 28: then, FIFOFUL=0, FIFOEMP=0

• 29 to 32: then, FIFOFUL=1, FIFOEMP=0

SDIO interrupt may be missed since SDIO interrupt processing is only done based on the IOINT (SDIOIST

[0]) status.

SDIO Interrupt Detecting: SDIO interrupt is a level interrupt on SDIO protocol, but the interrupt generation

logic detects the edge of DAT1 signal inside the host controller.

SDIO Interrupt Masking: The SDIO Interrupt may be enabled or disabled by the SDIO stack at any time.

SDIO Interrupt Status Clearing: SDIO interrupt status may not be cleared in an atomic sequence since a

pending interrupt has to be cleared not only on the host controller but also on the SDIO module.

To guarantee that the SDIO interrupt is not missed, the host controller has to check the IOINT

(SDIOIST[0]) status register as well as sample the DAT1 signal by checking the DAT1(SDIOST0[1-0])

status register at a certain condition.

The following is a suggested sequence for properly handling the SDIO interrupt:

1. SDIO stack informs the SDIO host controller to enable or unmask the SDIO interrupt.

2. SDIO host controller enables or unmasks the SDIO interrupt. Before enabling the SDIO interrupt, the

SDIO host controller software has to first sample the DAT1 signal (INTPRD==1 && DAT1==1) to make

sure that the pending interrupt is reported to the SDIO stack and then to the SDIO client/function

driver.

Note: SDIO interrupt is enabled at the request of the client/function driver of the SDIO stack. SDIO

interrupt needs to be enabled both on the host controller and the SDIO card which may not happen in

an atomic way. By the time the host controller enables the interrupt, the SDIO interrupt may be already

pending. The SDIO controller can not detect interrupt pending before the interrupt is enabled on the

controller.

3. When the SDIO interrupt is detected by the SDIO controller, the SDIO ISR has to process the SDIO

interrupts in the following sequence:

•

Check and clear SDIO interrupt status IOINT(SDIOIST[0]) immediately.

•

Mask the SDIO interrupt on the SDIO host controller by setting IOINTEN (SDIOIEN[0]) =0.

•

Notify the Interrupt event first to the SDIO stack and then to the SDIO client/function driver.

Note: The clearing of the SDIO interrupt on the SDIO card and SDIO controller does not happen in

an atomic way. To mask the SDIO interrupt, it has to be ensured that the interrupt is not mistakenly

detected by the host controller again. In addition, the client/function driver of the SDIO stack can

therefore control the occurrence of interrupt and also the readiness to process the interrupt.

4. The SDIO stack client/function driver clears the SDIO interrupt status on the SDIO card.

JESD22-A114D, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM), test results

indicate that the TMS320DM335 device's electrostatic discharge (ESD) sensitivity classification is Class 0

due to 4 reserved pins (BGA ID: J1, K1, L1, M1). All other pins meet the Texas Instruments design goal

ESD testing classification of Class 2. No workaround is required. Standard ESD-sensitivity device handling

procedures provide sufficient protection.

JESD22-C101C, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand

Thresholds of Microelectronic Components, testing was also conducted and results demonstrated that the

TMS320DM335 device's charged-device model (CDM) sensitivity classification is Class III (500 to 1000 V).

These results are consistent with the Texas Instruments CDM design goal.

8

TMS320DM335 Digital Media System-on-Chip (DMSoC)

SPRZ287A – July 2008 – Revised October 2008

Silicon Revision 1.1

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