SPIx_CLK

SPIx_SIMO

(a)Write(8or16−bit)

SPIDAT1.CSHOLD=1

(c)write(8or16−bit)

SPIDAT1.CSHOLD=0

(d)writeof

0x5678toSPIDAT1[15:0]

(b)writeof

0x1234toSPIDAT1[15:0]

(a) (b)

(c)

(d)

SPI_ENx

SPIx_CLK

SPIx_SIMO

(a)WriteSPIDA T1

=0x10001245

(CSHOLD=1)

(c)WriteSPIDA T1.CSHOLD=0

using8or16bitwrite.

(donotwritetoSPIDA T1[15:0])

(b)WriteSPIDA T1

=0x10005678

(CSHOLD=1)

(a)

(b)

(c)

SPI_ENx

SPIx_CLK

SPIx_SIMO

(a)Write(8or16−bit)

SPIDAT1.CSHOLD=1

(d)write(8or16−bit)

SPIDAT1.CSHOLD=0

(c)writeof

0x5678toSPIDAT1[15:0]

(b)writeof

0x1234toSPIDAT1[15:0]

(a) (b)

(c)

(d)

SPI_ENx

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Advisory 1.1.8 — SPI Master Mode: Extra Step Required to Use CSHOLD

Both Figure 2 and Figure 3 assume that SPIDAT1 is written using a single 32-bit write

instruction. If SPIDAT1 is instead written using an 8-bit or 16-bit instruction to write to the

CSHOLD field, followed by a 16-bit write to the transmit shift register field of SPIDAT1,

then what actually occurs is illustrated in Figure 4. This is the same case illustrated in

Figure 3 except that the de-assertion of SPI_ENx lasts for the duration between writing a

'0' to the CSHOLD field and writing new data to the transmit shift register.

Figure 4. Actual CSHOLD Behavior–Halfword Writes to SPIDAT1

Workaround(s)

For each word in the sequence of words during which SPI_ENx should be held low, write

to the SPIDAT1 register with the CSHOLD bit set to '1'. Follow this by a write to only the

CSHOLD field of SPIDAT1, setting CSHOLD = 0 to de-assert SPI_ENx. See Figure 5 for

an illustration.

Figure 5. Workaround Assuming 32-Bit Writes to SPIDAT1 Followed by a Write Only to CSHOLD

Alternatively, only write to the SPIDAT1 CSHOLD field before and after the transfer to

toggle the SPI_ENx pin. During the transfer, write only to the data field of SPIDAT1[15:0]

using 16-bit (halfword) write commands. For an illustration, see Figure 6.

Figure 6. Workaround Assuming Halfword Writes to SPIDAT1

SPRZ287A – July 2008 – Revised October 2008

TMS320DM335 Digital Media System-on-Chip (DMSoC)

19

Silicon Revision 1.1

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